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| M80C51FB CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER Military M80C51FB M80C51FB-16 Y Y Y 3 5 MHz to 12 MHz VCC e 5V g20% 3 5 MHz to 16 MHz VCC e 5V g20% Y Y Y Three 16-Bit Timer Counters Programmable Clock Out Programmable Counter Array with High Speed Output Compare Capture Pulse Width Modulator Watchdog Timer capabilities Up Down Timer Counter 256 Bytes of On-Chip Data RAM Boolean Processor ONCE (On-Circuit Emulation) Mode Available in 40-pin CERDIP and 44-pin Leadless Chip Carrier Packages Gull Wing and J-Lead Packages also Available 32 Programmable I O Lines 7 Interrupt Sources Programmable Serial Channel with Framing Error Detection Automatic Address Recognition TTL and CMOS Compatible Logic Levels 64K External Program Memory Space 64K External Data Memory Space MCS 51 Microcontroller Fully Compatible Instruction Set Power Saving Idle and Power Down Modes Military Temperature Range b 55 C to a 125 C (TC) Y Y Y Y Y Y Y Y Y Y Y Y MEMORY ORGANIZATION PROGRAM MEMORY The M80C51FB can address up to 64K of program memory external to the chip DATA MEMORY This microcontroller has a 256 x 8 on-chip RAM In addition it can address up to 64K bytes of external data memory The Intel M80C51FB is a single-chip control-oriented microcontroller which is fabricated on Intel's reliable CHMOS III-E technology Being a member of the family of MCS 51 microcontrollers the M80C51FB uses the same powerful instruction set has the same architecture and is pin for pin compatible with the existing MCS 51 microcontroller family of products The M80C51FB is an enhanced version of the M80C51 Its added features make it an even more powerful microcontroller for applications that require Pulse Width Modulation High Speed I O and up down counting capabilities such as motor control or fin actuation It also has a more versatile serial channel that facilitates multi-processor communications October 1994 Order Number 271172-002 M80C51FB 271172 - 1 Figure 1 M80C51FB Block Diagram 2 M80C51FB Port 0 Port 0 is an 8-bit open drain bidirectional I O port As an output port each pin can sink several LS TTL inputs Port 0 pins that have 1's written to them float and in that state can be used as high-impedance inputs Port 0 is also the multiplexed low-order address and data bus during accesses to external Program and Data Memory In this application it uses strong internal pullups when emitting1's and can source and sink several LS TTL inputs Port 1 Port 1 is an 8-bit bidirectional I O port with internal pullups The Port 1 output buffers can drive LS TTL inputs Port 1 pins that have 1's written to them are pulled high by the internal pullups and in that state can be used as inputs As inputs Port 1 pins that are externally being pulled low will source current (IIL on the data sheet) because of the internal pullups In addition Port 1 serves the functions of the following special features of the M80C51FB 271172 -2 DIP Port Pin P1 0 P1 1 P1 2 P1 3 P1 4 P1 5 P1 6 P1 7 Alternate Function T2 (External Count Input to Timer Counter 2) T2EX (Timer Counter 2 Capture Reload Trigger and Direction Control) ECI (External Count Input to the PCA) CEX0 (External I O for Compare Capture Module 0) CEX1 (External I O for Compare Capture Module 1) CEX2 (External I O for Compare Capture Module 2) CEX3 (External I O for Compare Capture Module 3) CEX4 (External I O for Compare Capture Module 4) LCC Gull Wing J-Lead 271172 -3 Figure 2 M80C51FB Pin Connections PIN DESCRIPTIONS VCC Supply voltage VSS Circuit ground Port 2 Port 2 is an 8-bit bidirectional I O port with internal pullups The Port 2 output buffers can drive LS TTL inputs Port 2 pins that have 1's written to them are pulled high by the internal pullups and in that state can be used as inputs As inputs Port 2 pins that are externally being pulled low will source current (IIL on the data sheet) because of the internal pullups 3 M80C51FB Port 2 emits the high-order address byte during fetches from external Program Memory and during accesses to external Data Memory that use 16-bit addresses (MOVX DPTR) In this application it uses strong internal pullups when emitting 1's During accesses to external Data Memory that use 8-bit addresses (MOVX Ri) Port 2 emits the contents of the P2 Special Function Register Port 3 Port 3 is an 8-bit bidirectional I O port with internal pullups The Port 3 output buffers can drive LS TTL inputs Port 3 pins that have 1's written to them are pulled high by the internal pullups and in that state can be used as inputs As inputs Port 3 pins that are externally being pulled low will source current (IIL on the data sheet) because of the pullups Port 3 also serves the functions of various special features of the M8051 Family as listed below Port Pin P3 0 P3 1 P3 2 P3 3 P3 4 P3 5 P3 6 P3 7 Alternate Function RXD (serial input port) TXD (serial output port) INT0 (external interrupt 0) INT1 (external interrupt 1) T0 (Timer 0 external input) T1 (Timer 1 external input) WR (external data memory write strobe) RD (external data memory read strobe) When the M80C51FB is executing code from external Program Memory PSEN is activated twice each machine cycle except that two PSEN activations are skipped during each access to external Data Memory EA External Access enable EA must be strapped to VSS in order to enable the device to fetch code from external Program Memory XTAL1 Input to the inverting oscillator amplifier XTAL2 Output from the inverting oscillator amplifier OSCILLATOR CHARACTERISTICS XTAL1 and XTAL2 are the input and output respectively of an inverting amplifier which can be configured for use as an on-chip oscillator as shown in Figure 3 Either a quartz crystal or ceramic resonator may be used More detailed information concerning the use of the on-chip oscillator is available in Application Note AP-155 ``Oscillators for Microcontrollers '' To drive the device from an external clock source XTAL1 should be driven while XTAL2 floats as shown in Figure 4 There are no requirements on the duty cycle of the external clock signal since the input to the internal clocking circuitry is through a divide-by-two flip-flop but minimum and maximum high and low times specified on the data sheet must be observed RST Reset input A high on this pin for two machine cycles while the oscillator is running resets the device An internal pulldown resistor permits a poweron reset with only a capacitor connected to VCC ALE Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory In normal operation ALE is emitted at a constant rate of the oscillator frequency and may be used for external timing or clocking purposes Note however that one ALE pulse is skipped during each access to external Data Memory PSEN Program Store Enable is the read strobe to external Program Memory 271172 - 4 C1 C2 e 30 pF g10 pF for Crystals e 10 pF for Ceramic Resonators Figure 3 Oscillator Connections 4 M80C51FB To properly terminate Power Down the reset or external interrupt should not be executed before VCC is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize (normally less than 10 ms) With an external interrupt INT0 and INT1 must be enabled and configured as level-sensitive Holding the pin low restarts the oscillator but bringing the pin back high completes the exit Once the interrupt is serviced the next instruction to be executed after RETI will be the one following the instruction that puts the device into Power Down 271172 -5 Figure 4 External Clock Drive Configuration IDLE MODE The user's software can invoke the Idle Mode When the microcontroller is in this mode power consumption is reduced The Special Function Registers and the onboard RAM retain their values during Idle but the processor stops executing instructions Idle Mode will be exited if the chip is reset or if an enabled interrupt occurs The PCA timer counter can optionally be left running or paused during Idle Mode DESIGN CONSIDERATION When the Idle Mode is terminated by a hardware reset the device normally resumes program execution from where it left off up to two machine cycles before the internal reset algorithm takes control Onchip hardware inhibits access to internal RAM in this event but access to the port pins is not inhibited To eliminate the possibility of an unexpected write when Idle is terminated by reset the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory POWER DOWN MODE To save even more power a Power Down Mode can be invoked by software In this mode the oscillator is stopped and the instruction that invoked Power Down is the last instruction executed The on-chip RAM and Special Function Registers retain their values until the Power Down Mode is terminated On the M80C51FB either a hardware reset or an external interrupt can cause an exit from Power Down Reset redefines all the SFRs but does not change the on-chip RAM An external interrupt allows both the SFRs and on-chip RAM to retain their values ONCE MODE The ONCE (``On-Circuit Emulation'') Mode facilitates testing and debugging of systems using the M80C51FB without the M80C51FB having to be removed from the circuit The ONCE Mode is invoked by 1) Pull ALE low while the device is in reset and PSEN is high 2) Hold ALE low as RST is deactivated While the device is in ONCE Mode the Port 0 pins go into a float state and the other port pins and ALE and PSEN are weakly pulled high The oscillator circuit remains active While the M80C51FB is in this mode an emulator or test CPU can be used to drive the circuit Normal operation is restored when a normal reset is applied Table 1 Status of the External Pins during Idle and Power Down Mode Idle Power Down Program Memory External External ALE 1 0 PSEN 1 0 PORT0 Float Float PORT1 Data Data PORT2 Address Data PORT3 Data Data NOTE For more detailed information on the reduced power modes refer to current 8-Bit Embedded Controller Handbook and Application Note AP-255 ``Designing with the M80C51BH '' 5 M80C51FB ABSOLUTE MAXIMUM RATINGS Case Temperature under Bias(6) Storage Temperature Voltage on EA VPP Pin to VSS Voltage on Any Other Pin to VSS Maximum IOL Per I O Pin b 55 C to a 125 C b 65 C to a 150 C 0V to a 13 0V b 0 5V to a 6 5V NOTICE This is a production data sheet The specifications are subject to change without notice WARNING Stressing the device beyond the ``Absolute Maximum Ratings'' may cause permanent damage These are stress ratings only Operation beyond the ``Operating Conditions'' is not recommended and extended exposure beyond the ``Operating Conditions'' may affect device reliability 15 mA Power Dissipation 1 5W (based on PACKAGE heat transfer limitations not device power consumption) Operating Conditions Symbol TC VCC fOSC Description Case Temperature (Instant On) Digital Supply Voltage Oscillator Frequency Min b 55 Max a 125 Unit C V MHz 40 35 60 16 D C CHARACTERISTICS Symbol VIL VIH VIH1 VOL Parameter Input Low Voltage Input High Voltage (Except XTAL1 RST) (Over Specified Operating Conditions) Min b0 5 Max 0 2 VCC b 0 1 VCC a 0 5 VCC a 0 5 03 0 45 10 Unit V V V V V V V V V V V V Test Conditions 0 2 VCC a 0 9 0 7 VCC Input High Voltage (XTAL1 RST) Output Low Voltage(5) (Ports 1 2 and 3) IOL e 100 mA (Note 1) IOL e 1 6 mA (Note 1) IOL e 3 5 mA (Notes 1 4) IOL e 200 mA (Note 1) IOL e 3 2 mA (Note 1) IOL e 7 0 mA (Note 1 4) IOH e b 10 mA IOH e b 30 mA IOH e b 60 mA VOL1 Output Low Voltage(5) (Port 0 ALE PSEN) 03 0 45 10 VOH Output High Voltage (Ports 1 2 and 3) VCC b 0 3 VCC b 0 7 VCC b 1 5 6 M80C51FB D C CHARACTERISTICS Symbol VOH1 (Over Specified Operating Conditions) (Continued) Min VCC b 0 3 VCC b 0 7 VCC b 1 5 b 75 Parameter Output High Voltage (Port 0 in External Bus Mode ALE PSEN) Logical 0 Input Current (Ports 1 2 and 3) Input leakage Current (Port 0) Logical 1 to 0 Transition Current (Ports 1 2 and 3) RST Pulldown Resistor Pin Capacitance Power Supply Current Active Mode 16 MHz Idle Mode 16 MHz Power Down Mode 16 MHz Max Unit V V V mA mA mA KX pF mA mA mA Test Conditions IOH e b 200 mA (Note 2) IOH e b 3 2 mA IOH e b 7 0 mA (Note 4) VIN e 0 45V 0 45V k VIN k VCC VIN e 2V IIL ILI ITL RRST CIO ICC g10 b 750 40 225 10 45 15 130 1 MHz 25 C (Note 3) NOTES 1 Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports 1 and 3 The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0 transitions during bus operations In applications where capacitance loading exceeds 100 pFs the noise pulse on the ALE signal may exceed 0 8V In these cases it may be desirable to qualify ALE with a Schmitt Trigger or use an Address Latch with a Schmitt Trigger Strobe input 2 Capacitive loading on Ports 0 and 2 cause the VOH on ALE and PSEN to drop below the VCC b 0 3 specification when the address lines are stabilizing 3 See Figures 5-8 for load circuits Minimum VCC for Power Down is 2V 4 Care must be taken not to exceed the maximum allowable power dissipation 5 Under steady state (non-transient) conditions IOL must be externally limited as follows 10mA Maximum IOL per port pin Maximum IOL per 8-bit port Port 0 26 mA Ports 1 2 and 3 15 mA 71 mA Maximum total IOL for all output pins If IOL exceeds the test condition VOL may exceed the related specification Pins are not guaranteed to sink current greater than the listed test conditions 271172 -6 All other pins disconnected TCLCH e TCHCL e 5 ns All other pins disconnected TCLCH e TCHCL e 5 ns 271172 - 7 Figure 5 ICC Load Circuit Active Mode Figure 6 ICC Load Circuit Idle Mode 7 M80C51FB 271172 - 8 All other pins disconnected Figure 7 ICC Load Circuit Power Down Mode VCC e 2 0V to 5 5V 271172 - 9 Figure 8 Clock Signal Waveform for ICC Tests in Active and Idle Modes TCLCH e TCHCL e 5 ns EXPLANATION OF THE AC SYMBOLS Each timing symbol has 5 characters The first character is always a `T' (stands for time) The other characters depending on their positions stand for the name of a signal or the logical status of that signal The following is a list of all the characters and what they stand for A Address C Clock D Input Data H Logic level HIGH I Instruction (program memory contents) L Logic level LOW or ALE P PSEN Q Output Data R RD signal T Time V Valid W WR signal X No longer a valid logic level Z Float For example TAVLL e Time from Address Valid to ALE Low TLLPL e Time from ALE Low to PSEN Low 8 M80C51FB A C CHARACTERISTICS (Over Specified Operating Conditions) EXTERNAL PROGRAM MEMORY CHARACTERISTICS Symbol 1 TCLCL Parameter Oscillator Frequency M80C51FB M80C51FB-16 ALE Pulse Width Address Valid to ALE Low Address Hold After ALE Low ALE Low to Valid Instruction In ALE Low to PSEN Low PSEN Pulse Width PSEN Low to Valid Instruction In Input Instruction Hold After PSEN Input Instruction Float After PSEN Address to Valid Instruction In PSEN Low to Address Float RD Pulse Width WR Pulse Width RD Low to Valid Data In Data Hold After RD Data Float After RD ALE Low to Valid Data In Address to Valid Data In ALE Low to RD or WR Low Address Valid to WR Low Data Valid before WR Data Hold after WR Data Valid to WR High RD Low to Address Float RD or WR High to ALE High 43 200 203 33 33 433 0 123 23 0 107 517 585 300 138 120 13 13 288 0 103 TCLCL b 40 400 400 252 0 65 350 398 238 3TCLCL b 50 4TCLCL b 130 TCLCL b 50 TCLCL b 50 7TCLCL b 150 0 TCLCL a 40 0 59 312 10 275 275 147 5 0 2TCLCL b 60 8TCLCL b 160 9TCLCL b 175 3TCLCL a 50 53 205 145 0 38 208 10 6TCLCL b 100 6TCLCL b 100 5TCLCL b 175 127 43 53 234 33 143 83 0 TCLCL b 25 5TCLCL b 115 20 85 23 33 150 TCLCL b 30 3TCLCL b 45 3TCLCL b 115 12 MHz Oscillator Min Max 16 MHz Oscillator Min Max Min 35 35 2TCLCL b 40 TCLCL b 40 TCLCL b 30 4TCLCL b 110 Variable Oscillator Max 12 16 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns TLHLL TAVLL TLLAX TLLIV TLLPL TPLPH TPLIV TPXIX TPXIZ TAVIV TPLAZ TRLRH TWLWH TRLDV TRHDX TRHDZ TLLDV TAVDV TLLWL TAVWL TQVWX TWHQX TQVWH TRLAZ TWHLH NOTE 7 Case temperatures are ``instant on'' 9 M80C51FB EXTERNAL PROGRAM MEMORY READ CYCLE 271172 - 10 EXTERNAL DATA MEMORY READ CYCLE 271172 - 11 EXTERNAL DATA MEMORY WRITE CYCLE 271172 - 12 10 M80C51FB SERIAL PORT TIMING - SHIFT REGISTER MODE Test Conditions Symbol (Over Specified Operating Conditions) 12 MHz Oscillator Min Max TXLXL TQVXH TXHQX TXHDX TXHDV Serial Port Clock Cycle Time Output Data Setup to Clock Rising Edge Output Data Hold after Clock Rising Edge Input Data Hold After Clock Rising Edge Clock Rising Edge to Input Data Valid 1 700 50 0 700 16 MHz Oscillator Min 0 75 492 8 0 492 Max Min 12TCLCL 10TCLCL b 133 2TCLCL b 117 0 10TCLCL b 133 Variable Oscillator Max ms ns ns ns ns Units Parameter SHIFT REGISTER MODE TIMING WAVEFORMS 271172 - 13 11 M80C51FB EXTERNAL CLOCK DRIVE Symbol 1 TCLCL Parameter Oscillator Frequency M80C51FB M80C51FB-16 High Time Low Time Rise Time Fall Time Min 35 35 20 20 20 20 Max 12 16 Units MHz ns ns ns ns TCHCX TCLCX TCLCH TCHCL EXTERNAL CLOCK DRIVE WAVEFORM 271172 - 14 A C TESTING INPUT Input Output Waveforms Float Waveforms 271172 - 15 AC Inputs during testing are driven at VCC b 0 5V for a Logic ``1'' and 0 45V for a Logic ``0'' Timing measurements are made at VIH min for a Logic ``1'' and VIL max for a Logic ``0'' 271172 - 16 For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH VOL level occurs IOL IOH t g20 mA 12 |
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